The present invention relates generally to the field of photovoltaic device construction and in particular the invention provides a low cost method of forming contacts to surfaces of silicon wafers and thin film devices.
A particular challenge for photovoltaic devices is to minimize recombination at the surfaces. With crystalline silicon devices, a common approach for passivating the surface is through thermal oxidation of the silicon surface. However, once the silicon dioxide layer is formed or grown or deposited onto the crystalline silicon surface, it is then an involved process to enable electrical contact to be made through the silicon dioxide layer to the underlying silicon material. In laboratory technologies, the most common approach for forming electrical contact through the silicon dioxide layer is through the use of photolithography and a mask aligner to facilitate the formation of openings in the silicon dioxide layer. Metal can then be applied which will only contact the silicon in the regions where the opening in the silicon dioxide have been formed. This approach allows precise location for the metal contacts as well as careful control over the silicon/metal contact area, which in general, if too large, will have detrimental consequences for device performance.
Most commercial solar cells use screen-printed metal contacts, which in general cannot be easily formed through a good quality surface passivating silicon dioxide layer. Such devices therefore normally avoid the use of silicon dioxide layers for surface passivation and therefore generally have relatively low open-circuit voltages compared to laboratory technologies. One commercial technology that does use a surface dielectric layer for surface passivation is the buried contact solar cell. These devices use laser scribing to penetrate through the dielectric layer to facilitate the formation of ohmic contacts to the underlying silicon. In this instance, the laser is used to perform an equivalent function as the photolithographic approaches for laboratory cells. One of the difficulties however, with both the laser grooving approach and the photolithographic approaches for forming metal contacts, is that in general, both require a heavy diffusion of the appropriate polarity of dopants to form a heavily doped region at the exposed silicon surface, to facilitate the formation of a low contact resistance interface between the silicon and the metal.
The challenge of forming ohmic contacts to the silicon material while simultaneously achieving good surface passivation for the remainder of the front and rear surfaces, becomes even more important for thinner devices. In general, thinning of bulk devices has the potential to improve performance and economics provided the surfaces are well passivated. Unfortunately however, all current commercial technologies sustain significant performance degradation when substrates are made thinner due to the relatively poor surface passivation. Ultimately, polycrystalline silicon devices need to be made with thickness"" below 10 microns to achieve the ultimate economic goals for this type of technology.
According to a first aspect, the present invention consists in a method of forming a connection to a region of first semiconductor material in a semiconductor device, the method comprising the steps of:
forming a passivation layer over the semiconductor surface to be contacted;
forming a layer of metal material over the passivation layer;
forming a layer of second semiconductor material over the layer of metal material, and heating the device, the second semiconductor material being selected to have a high mobility in the metal material at a temperature below the eutectic temperature of an alloy of the metal material and the second semiconductor material, the second semiconductor material being suitable for making electrical connection to the first semiconductor material, and the metal being selected to reduce at least weakened areas of the passivation layer at temperatures below the eutectic temperature, to thereby form openings in the passivation layer and the heating step including heating the device to a temperature below the metal material/second semiconductor material eutectic temperature at which the metal reduces the passivation layer at least in weakened areas of the passivation layer, the second semiconductor material being absorbed by the metal material, and migrating through the metal material during the heating step to be deposited on the passivation layer by solid phase epitaxial growth whereby the semiconductor material growth commences at nucleation sites on the semiconductor surface in the openings formed in the passivation layer where the passivation layer has been reduced by the metal layer.
According to a second aspect, the present invention consists in a method of forming a connection to a region of first semiconductor material in a semiconductor device, the method comprising the steps of:
forming a layer of second semiconductor material over a surface of the first semiconductor material to which the connection is to be made;
forming a passivation layer over the layer of second semiconductor material;
forming a layer of metal material over the passivation layer, the second semiconductor material being selected to have a high mobility in the metal material at a temperature below a eutectic temperature of an alloy of the metal material and the second semiconductor material, and the second semiconductor material being suitable for making electrical connection to the first semiconductor material; and
heating the device,
the metal being selected to reduce at least weakened areas of the passivation layer at temperatures below a eutectic temperature of an alloy of the metal material and the first semiconductor, to thereby form openings in the passivation layer, and the heating step including heating the device to a temperature, which is below the metal material/second semiconductor material eutectic temperature but at which the metal reduces the passivation layer at least in weakened areas of the passivation layer, and at which the second semiconductor material is absorbed by the metal material and the metal material migrates through the second semiconductor material until it contacts the surface of the first semiconductor material and whereafter the second semiconductor material absorbed by the metal material is deposited on the the surface of the first semiconductor material by solid phase epitaxial growth, the semiconductor material growth commencing at nucleation sites on the first semiconductor surface in areas in the region of the openings formed in the passivation layer where the passivation layer has been reduced by the metal layer.
Preferably, the first semiconductor material at the surface to which the contact is to be made, is a crystalline silicon material (either polycrystalline or single crystal material).
The material of the second semiconductor material layer is preferably amorphous silicon material, the metal is preferably aluminium and the heating step is preferably performed at a temperature less than the aluminium/silicon eutectic temperature of 577xc2x0 C.
According to a third aspect, the present invention consists in a method of forming a contact on a crystalline silicon semiconductor surface, the method comprising the steps of:
forming an oxide passivation layer over the crystalline semiconductor surface;
forming an aluminium layer over the passivation layer;
forming an amorphous silicon layer over the aluminium layer and heating the device to a temperature at which reduction commences in the passivation layer to form an opening through the passivation layer to expose the crystalline silicon surface, and silicon from the amorphous layer is dissolved in the metal layer and rapidly migrates through the metal layer to become a source for solid phase epitaxial growth of silicon at nucleation sites on the exposed crystalline silicon surface, whereby contact to the crystalline silicon surface is made via the epitaxially grown silicon in the openings in the passivation layer and the metal layer.
According to a fourth aspect, the present invention consists in a method of forming a contact on a surface of a crystalline silicon semiconductor material, the method comprising the steps of:
forming a layer of amorphous silicon material over the surface of the crystalline semiconductor material to which the contact is to make connection;
forming an oxide passivation layer over the layer of amorphous silicon material;
forming an aluminium layer over the passivation layer; and
heating the device to a temperature at which reduction commences in the passivation layer, to form an opening through the passivation layer and to expose the amorphous silicon layer, the amorphous silicon then being dissolved in the metal layer and the metal material rapidly migrates through the amorphous silicon layer until it contacts the surface of the crystalline semiconductor material after which the metal material becomes a source for solid phase epitaxial growth of silicon at nucleation sites on the crystalline silicon surface contacted by the metal material, whereby contact to the crystalline silicon surface is made via the aluminium layer and the epitaxially grown silicon in the openings in the passivation layer.
Preferably, at least in regard to the first and third aspects of the invention the passivation layer is formed by oxidization of the crystalline silicon surface.
Preferably also, in regard to the first and third aspects of the invention, the heating step is performed in two stages, the first stage being before commencement of the deposition of the final semiconductor layer (i.e., the amorphous silicon layer) such that the reduction of the passivation layer (i.e., the oxide layer) is well advanced before the amorphous silicon is absorbed into the metal layer.
The second heating stage is used to speed the migration of the semiconductor material through the metal layer and to enhance the epitaxial growth and is preferably performed during or after the step of depositing the final semiconductor layer. This second heating stage can be coincidental with the step of deposition of the final semiconductor layer as, for example, the temperature at which a Plasma Enhanced Chemical Vapour Deposition (PECVD) chamber or sputtering chamber may operate to deposit this layer can be chosen to be suitable for the epitaxial growth process.
While embodiments of the invention will be described with reference to silicon dioxide, other oxides can potentially be used as a passivation layer as also can a range of alternative dielectrics with the primary requirement being that the aluminium or alternative metal is able to penetrate through the corresponding dielectric to facilitate epitaxial growth of silicon from the existing semiconductor surface (e.g. Silicon or polycrystalline silicon surface). A range of metals (in addition to aluminium) can be used for metal mediated solid phase epitaxial growth and are suitable for use in embodiments of the invention.
In embodiments of the invention, other dopants may replace aluminium and can potentially lead to the growth of n-type material, therefore making it feasible to apply the invention with the reverse polarity for all layers of semiconductor material described hereinafter and shown in the figures. The preferred range of passivation layer thickness is from 2 to 400 nanometers. However, passivation layer thickness from outside this range may also function satisfactorily in some circumstances.
When forming a continuous layer for the solid phase epitaxially grown p-plus material, it is preferable to use similar volumes of amorphous silicon material to the volume of metal material previously deposited (i.e. similar thickness layers). The preferred dimensions for both the metal layer and the epitaxially grown layer are in the order of 0.6 microns. However, embodiments have been successfully fabricated using aluminium layers ranging from 10 nanometers to 1 micron, with corresponding amorphous silicon layers of similar dimensions, when trying to form continuous layers of solid phase epitaxially grown material. In each case, reduced volume of amorphous silicon deposition relative to the aluminium deposition will cause the formation of structures where the p-plus material is only grown in localized regions which can have significant advantages for some devices.
Throughout this specification the word xe2x80x9ccomprisexe2x80x9d, or variations such as xe2x80x9ccomprisesxe2x80x9d or xe2x80x9ccomprisingxe2x80x9d, will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed in Australia before the priority date of each claim of this application.